Static random access memory (SRAM) cells can have rapid access times, as compared to other memory types, and so can serve as important storage elements in integrated circuit devices. Various conventional SRAM cells are known. FIG. 10A shows a conventional six transistor (6T) SRAM cell 1001, which can include n-channel and p-channel transistors pairs (M101/M103, M105/M107) each in a CMOS inverter configuration. The CMOS inverters are cross-coupled between two nodes (N100, N101) to form a latch. Thus, nodes N100/N101 will be latched at complementary values (i.e., N100 high, N101 low, or vice versa). 6T SRAM cell 1001 also includes two access transistors M109/M111 which connect nodes N100/N101 to bit lines BLB and BL, respectively.
FIG. 10B shows an integrated circuit layout for a 6T SRAM cell like that of FIG. 10A. Like items are identified with the same reference characters. Because a 6T SRAM has both p-channel (i.e., latch pull-up) transistors and n-channel (i.e., latch pull-down) transistors, the memory cell can require substrate portions of different conductivity types (e.g., n-well for p-channel devices). As a result, a conventional 6T SRAM cell requires that some area be dedicated to well isolation or other similar structures.
Other SRAM cells are also known.
FIG. 11 shows a conventional four transistor (4T) SRAM cell 1101, which can include an n-channel transistors pair (M111/M113) cross-coupled between two nodes (N110, N111), as well as two pull-up resistors R111 and R113. Pull-up resistors (R111/R113) can be connected between the nodes N110/N111, respectively, and a power supply voltage VDD. In this arrangement, nodes N110/N111 can be latched between complementary values. Conventional 4T SRAM cell 1101 can also include two access transistors M115/M117 which connect nodes N110/N111 to bit lines BLB and BL, respectively. Pull-up resistors R111/R113 are typically patterned from a layer of polysilicon.
While conventional 4T SRAM cell 1101 can provide a more compact cell size than a 6T SRAM cell, if the pull-up resistors (R111/R113) are made from the same layer as the transistor gates additional spacing constraints can be imposed on the cell. Further, polysilicon pull-up resistors can require additional processing steps, such as doping in order to increase their resistance. Still further, polysilicon resistors can require additional process steps and/or complexity, such as a dual polysilicon process and/or the use of “buried” contacts to connect pull-up resistors to substrate areas.